The invention relates to a charge-coupled device comprising a memory of the series-parallel-series type having a series input register and a series output register as well as a parallel section located between these registers, for each line of bits stored in the parallel section the series input register being filled n successive times with a subline of bits in such a manner that the bits of one subline are stored between the bits of another subline in the parallel section.
Charge-coupled devices of this type are described inter alia in the chapter "Interlaced SPS" on page 200 ff. of the book "Charge-Coupled Devices and Systems" of Howes and Morgan, published by John Wiley and Sons Ltd., Edition 1980. By the use of the interlacing principle, according to which each line in the parallel section is read into the series input register in the form of several sublines, which are joined in the parallel section to form a whole line, the number of parallel registers per stage of the series registers can be increased. Thus, with a given line length, the length of the series registers can be limited and hence the size of the required crystal surface area can be limited. Moreover, the number of rapid transporting steps taking place in the series registers can be limited.
A specific application of SPS memories is described inter alia in the article "A Digital Field Memory for Television Receivers" of M. J. Pelgrom et al in I.E.E.E. Transactions on Consumer Electronics, Vol. CE-29, No. 3, August 1983, p. 242/248. In the system described here, the video information is supplied in digital form, i.e. 7 bits, parallel to 7 308 kbit memories. Each memory (chip) is in turn composed of 8 SPS blocks, into which the information supplied is read in demultiplexed form. The construction of the memories is such that information (bits) of two television lines is stored in each line of each block. For transferring bits from the series input register to the parallel section, use may be made of the horizontal line fly-back time (about 12 .mu.sec).
In general, in an SPS memory, in which the length of the series registers amounts to N bits, the clock frequency f.sub.p of the parallel section will be much higher than the clock frequency fs of the series registers, as a result of which the dissipation will take place for the major part in the series registers. For this reason, a further reduction of the length of the series registers would be desirable.
Another reason for reducing the length of the series registers may be found in a possible saving in area. The surface area occupied by the parallel section will depend essentially only upon the storage capacity and will therefore substantially not vary by shortening of the series registers. The saving in area is obtained in that the area occupied by the series registers and the associated wiring of clock lines and the like and the area occupied by the de-interlacing electrodes are reduced.
As is further known, charge losses always occur during the charge transport in charge-coupled devices. These charge losses are larger as the rate of transport increases and will therefore be largest in the series registers. This may be a third reason for reducing the length of the series registers to a minimum.